In 1988, I had the privilege of delivering the inaugural presentation at the VLSI/CAD Symposium. Throughout the decades, I have been privileged to contribute to this dynamic community, bearing witness to the remarkable evolution of our semiconductor industry. As I conclude my 40-year academic journey, I am compelled to impart insights gleaned from steering my final semiconductor moonshot project, generously supported by MOST.

Reflecting on this endeavor, I intend to share experiences and lessons learned. Key themes encompass hardware-aware network design, navigating the realms of international collaboration, harnessing the catalytic power of open-source initiatives, and fostering fruitful partnerships with industry players and startups alike. Additionally, I aim to offer practical recommendations tailored to funding agents, principal investigators, and reviewers, aimed at optimizing the success and impact of future ventures in semiconductor innovation.

With profound gratitude for the opportunities afforded and the camaraderie shared within this vibrant community, I eagerly anticipate the exchange of ideas and insights to come.

Dr. Youn-Long Lin, a distinguished figure in Computer Science, earned a PhD from the University of Illinois at Urbana-Champaign in 1987. Over 36 years at the National Tsing Hua University, he progressed from Associate Professor to Chair Professor and Department Head, leaving an indelible mark on academia. As Vice President of Research & Development, Dr. Lin steered the institution's research initiatives. He extended his influence globally as a Guest Professor at Waseda University and Peking University.

A leading researcher, Dr. Lin's expertise spans physical design automation, high-level synthesis, video codec architecture, and neural network architecture. Beyond academia, he co-founded and served as CTO of Global Unichip Corp, founded Neuchips Corp, and played a pivotal role in founding the Chip Implementation Center (CIC) and the MOE VLSI design education program, fostering collaborative innovation.

Lab-on-a-Chip (LoC) is a well-known sample preparation technique for bio-medical tests using non-silicon-based approaches. Due to the features of customized micro channels, LoC-based devices has been proved successfully in many test cases with better cost-efficiency. In this talk, we’ll first introduce how LoC can be realized by standard CMOS technology with field programmability, leading to the capability of adjustable micro-channels for different sample tests. Then several Lab procedures are integrated into the proposed CMOS LoC (BioFPGA), including location sensing, microfluidics operations, thermal cycle, magnetic operations, ..etc. Furthermore target bio-protocols can be derived for different bio-marker tests to achieve precise and automatic test solutions. Finally some test results, together with research opportunities, will be reported using the proposed bioFPGA chips and the developing devices for mobile nuclei acid test applications.

李鎮宜於1982年在台灣新竹的國立交通大學（NCTU）獲得學士學位，並分別於1986年和1990年在比利時魯汶天主教大學（KUL）獲得碩士和博士學位，專業均為電機工程。

從1986年到1990年，他在比利時IMEC/VSDM工作，從事DSP架構合成領域的工作，1991年2月，他加入了電子工程系，並於2003年至2006年擔任系主任。2007年至2010年，他擔任國立交通大學研究與發展辦公室主任。2000年至2003年，他擔任台灣國家晶片實驗中心的主任。2003年至2005年，他擔任國家科學委員會工程組微電子計劃的協調員。目前。他擔任國家智慧電子計劃的聯合計畫主任，並擔任國立交通大學電子工程系特聘教授。他的研究興趣主要包括用於高通量DSP應用的VLSI算法和架構。他還積極從事微感測、低功耗片上系統和大數據分析等各個方面的研究。

李博士目前為國立陽明交通大學的副校長，且有擔任IEEE ASSCC技術程序委員會成員、IEEE VLSI Symposium JFE Circuits程序委員會成員和IEEE TCAS-II副編輯。他曾擔任IEEE ISSCC的程序委員會成員（2004年至2006年）、DATE技術程序委員會成員（2006年至2007年）以及IEEE Circuits and Systems（CAS）學會台北分會的前任主席。他曾於2007年、2008年分別獲得國家科學委員會和2009年經濟部的技術轉移傑出獎。2009年，獲得國家科學委員會的優秀研究獎。

To achieve the power, performance, and area (PPA) target in modern semiconductor design, the trend to go for More-than-Moore heterogeneous integration by packing various components/dies into a package becomes more obvious as the economic advantages of More-Moore scaling for on-chip integration are getting smaller and smaller. In particular, we have already encountered the high cost of moving to more advanced technology and the high fabrication cost associated with EUV, mask, process, design, EDA, etc. Heterogeneous integration refers to integrating separately manufactured components into a higher-level assembly (such as Chip-on-Wafer-on-Substrate (CoWoS) and even multiple packages in a PCB) that provides enhanced functionality and improved operating characteristics. Unlike the on-chip designs with relatively regular components and wirings, the design problem for heterogeneous integration often needs to handle arbitrary component/board shapes, diverse metal line widths, and different spacing requirements between components, wire metal, and pads, with multiple cross-physics domain considerations such as system-level, physical, electrical, mechanical, thermal, and optical effects, which are not well addressed in the traditional chip design flow. In this talk, we first introduce popular heterogeneous integration technologies and options, their modeling and induced design problems, survey key published techniques, and provide future research directions for modern EDA and design problems in heterogeneous integration.

Yao-Wen Chang received a B.S. degree from National Taiwan University (NTU), Taiwan, in 1988 and M.S. and Ph.D. degrees from the University of Texas at Austin in 1993 and 1996, respectively, all in computer science.

Dr. Chang is a Fellow of the ACM and the IEEE. He is a Past President of the IEEE Council on Electronic Design Automation (CEDA) after serving as the first non-US/-European CEDA president in 2020/2021. He is currently a Distinguished Professor of the Dept. of Electrical Engineering at NTU after serving as the Dean of the College of Electrical Engineering and Computer Science 2018-2024. His current research interests lie in electronic design automation. He has co-authored one textbook on Electronic Design Automation (Elsevier/Morgan Kaufmann, 2009) and one research book on routing (Springer, 2007), 16 U.S. patents, and more than 360 ACM/IEEE conference/journal papers in these areas (93 papers in DAC [#1 worldwide], 76 papers in ICCAD [#2 worldwide], and 82 papers in TCAD [#4 worldwide]), including highly cited works on floorplanning, placement, routing, design for manufacturability, and FPGA. He published the world’s most DAC+ICCAD+TCAD papers. His NTUplace3 placer was the core engine of the popular Digital Custom Placer of SpringSoft, acquired by the #1 EDA vendor, Synopsys, in 2012 for USD 400M+. His NTUplace4 received three champions at top EDA contests and is the core engine of the leading placer, MaxPlace, by Maxeda, which he co-founded in 2015, and acquired by Synopsys in 2023.

Dr. Chang received four awards at the 50th ACM/IEEE DAC in 2013 for the DAC Prolific Author (now 93 papers, the all-time #1 prolific author), the Longest Publication Streak (now 26 years from 1999 to now, #1 worldwide), etc. Dr. Chang has received 23 top-3 international EDA contest awards (worldwide #1) with seven champions. He has received eleven Best Paper Awards (including DAC’17), the 2007 ICCAD Professor Margarida Jacome Memorial Grant, and the 2020 ASP-DAC Prolific Author Award. He has received two NTU distinguished teaching awards (the highest honor for the top 1% of teachers for ten years), nine NTU excellent teaching awards, and many domestic research awards, including the Distinguished Research Fellow from the National Science and Technology Council and the Academic Award from the Ministry of Education.

Dr. Chang has been an associate editor of IEEE TCAD, IEEE TVLSI, IEEE Design & Test of Computers, etc. He has served as the general/program chair of ICCAD and ISPD and the program chair of ASP-DAC and FPT, and on the IEEE CEDA, DAC, and ICCAD Executive Committees, and the ASP-DAC Steering Committee. He is a recipient of the 2015 IEEE CEDA Outstanding Service Award and the 2012 ACM Recognition of Service Award. He has served as the chair of the EDA Consortium of Taiwan’s Ministry of Education. He was the founding chair of Taiwan’s CAD Contest 1999-2001, becoming the most popular CAD Contest at ICCAD since 2012. He has been an independent board director of Genesys Logic and MediaTek (starting May 2024) and a technical consultant for MediaTek, Realtek, and Faraday Technology.