1. 記憶體市場簡介
2. 南亞科技簡介
3. 薪資福利簡介

學歷：淡江大學 經濟學系 碩士畢業
經歷：
104年~至今 南亞科技股份有限公司/人力資源處 薪資任用部 資深管理師
101年~104年 Johnson & Johnson 壯生醫療器材股份有限公司/ASP消毒滅菌 資深業務

GLOBAL UNICHIP CORP. (GUC) leads in advanced ASIC services, offering comprehensive design solutions from 'spec-in' to turn-key manufacturing. Join our enlightening lunch talk on GUC, gain insights into dynamic opportunities, and explore thrilling career prospects. Don't miss out on broadening your understanding of the exciting realm of GUC!

Kuan-Ting Chen currently serves as a manager at Global Unichip Corp (GUC), where he specializes in physical design implementation, methodology, and PPA analysis across advanced process nodes. His expertise has been crucial in propelling numerous high-performance computing (HPC) projects to success and has been pivotal in delivering comprehensive PPA assessments and Design-Technology Co-Optimization (DTCO) for clients. Mr. Chen's association with GUC commenced in 2013. Following a brief hiatus, he rejoined the company in 2024 to lead a team dedicated to enhancing physical implementation methodologies and workflows. He holds an M.Sc. in Electronics Engineering from National Chiao Tung University, which underpins his profound academic foundation in the field.

In this talk we introduce TSMC's 3DFabric^TM that covers a wide range of applications for the next generation of cost effective and ultra-large integration IC designs, as we adapt to the slowing of monolithic IC scaling and the increasing cost per transistor. However, turning a monolithic IC design into 3DIC is not free, in particular, die-to-die communication incurs power, performance and area overheads that need to be carefully studied and managed. This talk will give an overview of the various types of popular die-to-die interfaces among chiplets, as well as an outlook to the future of die-to-die scaling trend as 3DIC technology advances.

Dr. King Ho Tam has been with TSMC since 2009 specializing in electrical sign-off methodology. He has been leading a team to enable efficient and accurate electrical sign-off methodologies for 3DIC including static timing analysis, IR drop, electromigration, signal and power integrity with leading EDA companies for internal testchips and world leading design houses, as well as design-technology co-optimization with process R&D to enhance 3DFabricTM for emerging 3DIC applications. He is currently the deputy director of Chip Implementation CAD Department under Design Technology Platform and has been elected as TSMC Academician. He has 17 US patents and 5 IEEE publications during his tenure at TSMC. Before joining TSMC, he worked for Cadence, IBM Watson Research and Intel to develop static timing analysis and optimization EDA software. He received PhD in Electrical Engineering from UCLA in 2008.