Industrial Session (2)

Tackling Advanced Analog FinFET Design/Layout Challenges with Brand New Methodologies



  • Scott Li
    • Application Engineer Director, Cadence Design Systems

  • 日期:2024年8月1日(四)
  • 時間:11:10 - 12:10
  • 地點:台中福容大飯店 櫻花廳

Abstract:

With the strong growth from AI, HPC, Automotive, 5G/6G, etc., the demand for more powerful IC is increasing significantly in recent years. To provide better performance, leveraging FinFET process is one of the key solutions and become a major challenge to Analog design. In this section, it will start from the challenges of migrating to FinFET process and how Cadence can help to overcome these challenges to bring new opportunities in the new world.


Biography:

Scott Li is Application Engineer Director of Mixed-Signal Platform at Cadence and in charge of all the support of Mixed-Signal design related products from front-end to back-end. Scott has over 13 years’ experience in EDA industry and his expertise is Mixed-Signal design flow and integration. Scott received his B.S. EE (2003) and M.S. EE (2005) from National Taiwan Univ. (NTU).